Planar process

One historian called it the most important innovation in the history of the semiconductor industry. The planar process—leaving a protective oxide layer in place on a silicon wafer rather than etching it away—seems almost trivially simple in retrospect. But this insight, recorded by Jean Hoerni at Fairchild Semiconductor in December 1957, made the integrated circuit possible and created the region we now call Silicon Valley.

The problem was reliability. Early transistors used the mesa process, which involved etching away the silicon dioxide layer to expose the semiconductor junctions. These exposed junctions degraded rapidly when contaminated by dust, moisture, or handling. Transistors that worked perfectly in the laboratory failed unpredictably in the field. For military and aerospace applications—Fairchild's primary customers—such unreliability was unacceptable.

Hoerni's insight was counterintuitive: instead of removing the oxide layer, leave it in place. Silicon dioxide acts as a natural passivation layer, protecting the sensitive p-n junctions beneath from contamination. The junctions would be formed by diffusing dopants through windows cut in the oxide, then the oxide would be allowed to regrow over the junctions. The result was a flat, protected surface—hence "planar."

The timing reveals how the adjacent possible constrains invention. Hoerni recorded his first expression of the planar concept on December 1, 1957—just two months after Fairchild's founding. But the idea sat dormant for over a year. Only after writing a patent disclosure in January 1959 did he demonstrate a working planar transistor that March. The insight required validation; the validation required time.

Hoerni filed his patent on May 1, 1959, and Fairchild introduced the 2N1613 planar transistor commercially in April 1960. The company licensed the process across the industry, spreading the technique to competitors—a decision that accelerated the entire semiconductor ecosystem rather than protecting a temporary monopoly.

The cascade from the planar process was immediate and profound. Robert Noyce, Hoerni's colleague at Fairchild, realized that if transistors could be fabricated with a flat oxide layer, multiple transistors could be interconnected on the same chip without the manual wiring that had plagued earlier integration attempts. His planar integrated circuit, also invented in 1959, followed directly from Hoerni's process innovation.

Late in 1959, Jay Last assembled a team at Fairchild whose efforts led to the development of Micrologic—the first planar integrated circuits and the forerunners of modern microelectronics. By 1960, the path from individual transistors to integrated circuits to microprocessors had become visible. The billion-transistor chips of today still rely on Hoerni's fundamental insight: protect the junctions, keep the surface flat, build up complexity layer by layer.

The geographic concentration matters. Fairchild Semiconductor was located in Mountain View, California, and its alumni—the "Fairchildren"—went on to found Intel, AMD, and dozens of other semiconductor companies, all clustered in the same region. The planar process did not just enable integrated circuits; it enabled Silicon Valley itself. The conditions that made Fairchild possible—Stanford engineering graduates, military contracts, venture capital—also made its successors possible. Path dependence locked in both the technology and the geography.